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Toshiba Memory Corporation and Synopsys Collaborate to Accelerate 3D Flash Memory Verification

Synopsys announced that it has collaborated with Toshiba Memory Corporation to accelerate the verification of Toshiba Memory Corporation's BiCS FLASH vertically stacked three-dimensional (3D) flash memory. By working closely with Toshiba Memory Corporation, Synopsys introduced innovative simulation algorithms in its FineSim Pro FastSPICE tool to address the increased design complexity of 3D NAND Flash memory. These new technologies improve simulation speed by an average of 2X, thereby reducing multi-day simulation runs to less than a day.

Compared to traditional Flash devices, 3D Flash devices have much larger memory arrays, more complex analog and programming circuits, and extensive power distribution network. Additionally, due to the stacked memory array structure, 3D Flash designs must deal with increased coupling effects due to layout parasitic elements. This increased complexity results in multi-day simulation times when using existing circuit simulation technology.

Through close collaboration with Toshiba Memory Corporation, the latest release of FineSim Pro FastSPICE delivers several key technologies specifically optimized for 3D Flash simulation, for efficient handling of massive array structures, large power distribution network, increased layout parasitic elements, and high-precision analog circuits.

"FineSim has been our signoff circuit simulator since early 2000. Our long collaboration with Synopsys has enabled us to develop best-in-class Flash memory products for a broad range of applications," said Shigeo (Jeff) Ohshima, Technology Executive SSD Application Engineering of Toshiba Memory Corporation. "By working closely with Synopsys we're able to deploy FineSim Pro for verification of our latest BiCS Flash memories and meet our stringent quality and reliability requirements."

"Advanced flash memory designs require extensive circuit simulation to ensure design robustness, reliability, and cost competitiveness," said Paul Lo, corporate vice president of Engineering in the Design Group at Synopsys. "Our team is committed to continuing our close collaboration with Toshiba Memory Corporation to deliver novel circuit simulation technologies to meet the challenging needs of simulating complex 3D NAND Flash memories and enable Super Chips with Synopsys."

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